1. Field of the Invention
The present invention relates to a plasma etching apparatus, plasma etching method, and computer readable storage medium, used for performing a plasma etching on a target substrate, such as a semiconductor substrate.
2. Description of the Related Art
For example, in the process of manufacturing semiconductor devices, plasma etching processes, which utilize plasma to etch a layer through a resist mask, are often used for forming a predetermined pattern on a predetermined layer disposed on a target substrate, such as a semiconductor wafer.
Although various plasma etching apparatuses for performing such plasma etching are present, parallel-plate plasma etching apparatuses of the capacitive coupling type are in the mainstream of them.
In general, a parallel-plate plasma etching apparatus of the capacitive coupling type includes a chamber with a pair of parallel-plate electrodes (upper and lower electrodes) disposed therein. While a process gas is supplied into the chamber, an RF (radio frequency) power is applied to at least one of the electrodes to form an electric field between the electrodes. The process gas is turned into plasma by the RF electric field, thereby performing plasma etching on a predetermined layer disposed on a semiconductor wafer.
Specifically, there is known a plasma etching apparatus in which an RF power for plasma generation is applied to the upper electrode to generate plasma, while an RF power for ion attraction is applied to the lower electrode (for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-173993 (Patent publication 1)). This plasma etching apparatus can form a suitable plasma state and realize an etching process with a high selectivity and high reproducibility.
In recent years, owing to the demands of higher speed of semiconductor devices, and increased miniaturization and higher integration degree of interconnection line patterns, it is promoted to utilize inter-level insulating films having a low dielectric constant, so as to decrease the parasitic capacitance of interconnection lines. Of the low dielectric constant films (Low-k films) of this kind, SiOC family films particularly attract attentions. An SiOC family film can be formed from a conventional SiO2 film by introducing methyl groups (—CH3) into Si—O bonds of the film, thereby mixing Si—CH3 bonds.
Where plasma etching is performed on an organic Low-k film, such as an SiOC family film, it is important to ensure a sufficient selectivity between the organic Low-k film and a mask layer or an underlying film. In general, a mixture gas based on a fluorocarbon gas is used as a process gas to provide a relatively high selectivity of a target film relative to an underlying film, but this is not enough to ensure a sufficient selectivity. In light of this problem, an etching method has been proposed for etching an SiOC family film, as described below, to improve the selectivity relative to a silicon nitride film (for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-270586 (Patent publication 2)). Specifically, plasma etching is performed on an SiOC family inter-level insulating film while a silicon nitride film used as a barrier layer of a Cu interconnection line is utilized as an underlying etching-stopper layer. In this method, C4F8/Ar/N2 is used as a process gas with a flow rate ratio of Ar set to be 80% or more, thereby improving the selectivity relative to the underlying film.
Further, another etching method has been proposed as described below (for example, Jpn. Pat. Appin. KOKAI Publication No. 2004-87875 (Patent publication 3)). Specifically, as in Patent publication 2 described above, plasma etching is performed on an SiOC family inter-level insulating film while a silicon nitride film is utilized as an underlying etching-stopper layer. This method comprises a first etching step of using CHF3/Ar/N2 as a process gas and a second etching step of using C4F8/Ar/N2 as a process gas, thereby improving the selectivity relative to both of the mask and silicon nitride film.
However, as described above, silicon nitride used for a barrier layer of a Cu interconnection line has good barrier properties, but has a high dielectric constant of 7.0. Accordingly, in order to sufficiently utilize the low dielectric constant property of a Low-k film, such as an SiOC family film, a barrier layer having a still lower dielectric constant is required. One of the materials for such a barrier layer is silicon carbide (SiC) having a dielectric constant of 3.5.
Where an SiC barrier layer having a low dielectric constant is used as an underlying etching-stopper layer for etching an etching target layer formed of a Low-k film disposed thereon, it is also necessary to ensure a sufficient etching selectivity between them. In general, SiC family films of this kind contain about 10% oxygen, and thus the composition thereof is similar to that of SiOC family Low-k films. A plasma etching process using a fluorocarbon process gas, as disclosed in Patent publications 2 and 3 described above, may be applied to a structure including an SiOC family Low-k film and an SiC layer. In this case, however, the margin for ensuring a sufficient etching selectivity between the film and layer is narrow and makes it difficult to etch the SiOC family Low-k film with a high selectivity and a high etching rate.
On the other hand, where etching of via holes or contact holes is performed in a parallel-plate plasma etching apparatus of the capacitive coupling type, a so-called micro-loading effect is undesirably caused, such that the etching rate varies depending on the size of holes, and makes it difficult to control the etching depth. Particularly, the etching rate is generally higher at a large area, such as a guard ring (GR), while the etching rate is generally lower in a smaller area which CF family radicals cannot easily get in.
Where no etching-stopper layer is disposed, the etching depth fluctuates due to the micro-loading effect, and carries over the fluctuations to subsequent steps, thereby deteriorating the uniformity of electric properties. Even where an etching-stopper layer is disposed, an over etching time needs to be prolonged, and thus brings about additional losses and fluctuations on the underlying layers, which adversely affect electric properties.
Conventionally, in order to solve the problems described above, the pressure inside a chamber is decreased to perform an etching process at a low pressure along with a low flow rate, so as to promote etching at, e.g., small via-holes. However, with decreases in the pressure and flow rate during a process, the selectivity relative to a mask and/or an underlying layer becomes smaller, thereby deteriorating the flexibility of the process.